Generally, the electrothermal transducer (heater) of a recording head mounted in a recording apparatus conforming to ink jet method and the driving circuit of the electrothermal transducer are formed on the same substrate by semiconductor process technology as disclosed in, for example, the specification of U.S. Pat. No. 6,290,334. Further, a recording head is proposed in which a digital circuit or the like for detecting a state of such a semiconductor substrate, e.g., a substrate temperature is formed on the same substrate in addition to the driving circuit, an ink supply port is disposed around the center of the substrate, and heaters are opposed to each other with the ink supply port interposed therebetween.
FIG. 6 is a diagram schematically showing the semiconductor substrate for such an ink jet recording head, namely, a semiconductor substrate for an ink jet recording head including a circuit for outputting a digital signal for detecting a temperature.
In FIG. 6, reference numeral 500 denotes a substrate where heaters and driving circuits are integrally formed by semiconductor process technology. Reference numeral 501 denotes a heater/driver array in which two or more heaters and driver circuits are arranged. Reference numeral 502 denotes ink supply ports for supplying ink from the backside of the substrate.
Reference numeral 503 denotes shift registers for temporarily storing print data to be recorded. Reference numeral 507 denotes decoder circuits each of which outputs a heater block selection signal for driving the heaters in the heater/driver array 501 for each heater block. Reference numeral 504 denotes input circuits each including a buffer circuit for inputting a digital signal to the shift register 503 and the decoder 507. Reference numeral 510 denotes input terminals including a terminal for supplying a logic device voltage Vdd, a terminal CLK for inputting a clock signal, and a terminal for inputting data such as print data.
FIG. 8 is a timing chart for explaining a series of operations of the transmission of print information to the shift register 503, the supply of current to the heater, and the driving of the heater.
Print data is supplied to DATA_A and DATA_B terminals in synchronization with a clock pulse inputted to the CLK terminal. The shift register 503 temporarily stores the supplied print data and a latch circuit stores the print data in response to a latch signal applied to a BG terminal. Thereafter, a block selection signal for selecting a heater group divided into desired blocks and the print data (device selection signal) having been stored in response to the latch signal are ANDed in a matrix manner, and heater current is applied in synchronization with an HE signal for directly determining a current driving time. The series of operations is repeated for each block to perform printing.
FIG. 7A is an equivalent circuit diagram showing one segment for supplying current to the heater for discharging ink. FIG. 7B is an equivalent circuit diagram corresponding to 1 bit in the shift register and the latch circuit which temporarily store image data to be printed.
The block selection signal inputted to an AND circuit 601 is transmitted from the decoder circuit 507 in order to select a heater group divided into timing blocks which can be driven with almost the same timing. The device selection signal inputted to the AND circuit 601 is based on an image signal which is transferred to the shift register 503 and then stored in response to the latch signal. In order to selectively turn on each segment according to print data, the block selection signal and the device selection signal are ANDed in a matrix manner by the AND circuit 601.
Reference numeral 605 denotes a VH power supply line serving as a power supply for driving the heater, reference numeral 606 denotes the heater, and reference numeral 607 denotes a driver transistor for passing current through the heater 606. Reference numeral 602 denotes an inverter circuit acting as a buffer in response to the output of the AND circuit 601. Reference numeral 603 denotes a VDD power supply line serving as the power supply of the inverter circuit 602. Reference numeral 608 denotes an inverter circuit acting as a buffer for receiving the buffer output of the inverter circuit 602. Reference numeral 604 denotes a VHT power supply line which acts as a power supply for supplying power to the buffer including the inverter circuit 608 and supplying the gate voltage of the driver transistor.
Generally, the inverter 602 and the shift register 503 or the like are digital circuits and are basically operated by a Lo/Hi pulse. Further, the interface of the original print information of the recording head and an applied pulse for driving the heater are also digital signals, and the signals are transmitted and received to and from the outside by a Lo/Hi logic pulse. These logic pulses generally have an amplitude of 0 V/5 V or 0 V/3.3 V. A power supply VDD of the digital circuit is supplied by one of these voltages. Therefore, a pulse having an amplitude of a VDD voltage is inputted to the AND circuit 601, passes through a buffer comprising the two-stage inverter circuit 602, and is inputted to the inverter circuit 608 of the subsequent stage.
The inverter circuit 608 of the subsequent stage is also a logical circuit but operates at a higher voltage than the inverter 602 of the previous stage.
It is preferable that the driver transistor 607 has a low resistance, that is, a low on-resistance in an on state. This is because power consumed by a part other than the heater is minimized, which makes it possible to prevent an increase in substrate temperature and stably drive the recording head. In the case where the driver transistor 607 has a high on-resistance, a voltage drop caused by the passage of heater current through this part increases and an excessively high voltage has to be applied to the heater, resulting in excessive power consumption.
In order to reduce the on-resistance of the driver transistor 607, a voltage applied to the gate of the driver transistor 607 has to be set high. For this purpose, the circuit of FIG. 7A requires a circuit for conversion into a pulse having an amplitude of a voltage higher than the voltage VDD. Thus, in the circuit of FIG. 7A, the power supply line 604 of a voltage VHT higher than the voltage VDD is prepared. A segment selection signal (a signal for selectively driving heaters) having been inputted by a pulse having an amplitude of the VDD voltage is converted into a pulse having an amplitude of the voltage VHT by a buffer circuit including the inverter circuit 608. After the conversion into the pulse having the amplitude of the voltage VHT, the pulse is applied to the gate of the driver transistor 607. In other words, as shown in FIG. 7A, signals are transmitted and received to and from the outside, and signal processing in the internal digital circuit is performed by the pulse having the amplitude of the voltage VDD (voltage for driving a logical circuit). Moreover, a circuit (pulse amplitude converter circuit) is added to each segment. The circuit converts the signal into the pulse having the amplitude of the voltage VHT (voltage for driving a device) immediately before the gate of the driver transistor 607 is driven.
Generally, the recording head has a plurality of segments arranged with a high density. Thus, for example, when the segments are arranged with a density of 600 dpi, the width of the segment is limited to about 42.3 μm in the arrangement direction. In the case where the circuits of FIG. 7A for driving the segments are all stored in this pitch, each of the segments requires a large area corresponding to the number of devices in a direction perpendicular to the arrangement direction. The area is larger than that of a configuration having a lower density of arrangement.
FIG. 9 is an equivalent circuit diagram showing a specific configuration of the pulse amplitude converter circuit of FIG. 7A. As shown in FIG. 9, the pulse amplitude converter circuit, particularly a level conversion part indicated by a dotted line comprises a number of transistors, which requires a large chip area.
In the case of the layout of the substrate for the recording head configured thus, the pulse amplitude converter circuit added for each segment increases the length of each segment, thereby increasing a chip size and cost. To be specific, in the foregoing layout, a chip expands in a direction perpendicular to a segment array and thus the chip considerably increases in size. Further, when a pulse amplitude converter circuit is added to each segment, for example, in the case of a recording head with 256 segments, the necessary number of buffer circuits is equivalent to at least 256 inverters. This configuration reduces yields and complicates a circuit configuration, thereby increasing cost.